This invention relates to a driving circuit for solid-state image sensor used in video cameras or electronic still cameras and a counter circuit used therein.
In video cameras and electronic still cameras, recently, solid-state image sensor are widely used as image pickup devices in order to achieve smaller size, lighter weight, higher picture quality, multiple functions and lower price. To drive the solid-state image sensor, it is necessary to feed television signals, in particular various driving signals synchronized with their synchronizing signals, to the solid-state image sensor.
FIG. 8 shows a basic configuration of a driving circuit for a solid-state image sensor as an elementary foundation for the invention. In FIG. 8 a reference clock signal supplied in a terminal 1 is fed into a first counter circuit 2 and a second counter circuit 3. The output of the first counter circuit 2 is delivered from a terminal 4 as a reference signal for horizontal scanning period. The output of the second counter circuit 3 is supplied to a first logic circuit 5 together with the output of the first counter circuit 2. The second coutner circuit 3 is reset by the output of the first logic circuit 5. The output of the second counter circuit 3 is decoded by a second logic circuit 6. As a result, a vertical transfer pulse used in signal processing or a driving signal of the solid-state image sensor (hereinafter commonly called a driving signal) is generated, and this driving signal is outputted from a terminal 7.
In the driving circuit for the solid-state image sensor shown in FIG. 8, a ring counter shown in FIG. 9 is used as the second counter circuit 3.
The ring counter shown in FIG. 9 is composed of cascade connection of D-type flip-flops 8 to 12, and is intended to feed a clock signal from a terminal 13 to each clock (CK) terminal of the flip-flops 8 to 12, and feed a reset signal from a terminal 14 to each reset terminal of the flip-flops 8 to 12.
FIG. 10 shows the clock signal supplied to the ring counter, the reset signal, the voltage waveform of each Q output of the D-type. flip-flops 8 to 12 corresponding to the clock signal, and the number of logic changes of the D-type flip-flops 8 to 12. In FIG. 10, (a) denotes the clock signal supplied to the terminal 13, (b) shows the reset signal-supplied to the terminal 14, (c) to (g) are voltage waveforms of the Q outputs of the D-type flip-flops 8 to 12, respectively, and (h) represents the number of logic changes of the Q outputs of the D-type flip-flops 8 to 12 corresponding to the clock signal. The number of logic changes shown in FIG. 10(h) is to express the number of changes, by the length of the vertical line, when the Q outputs of the flip-flops 8 to 12 are changed simultaneously at the rising or falling timing of the clock signal.
In the ring counter shown in FIG. 9, after all D-type flip-flops 8 to 12 are reset as the reset signal (b) becomes high level the clock signal (a) is fed to the clock (CK) terminal of the flip-flops 8 to 12. As a result, counter outputs Q8 to Q12 appear at the Q output terminals of the D-type flip-flops 8 to 12.
Here, taking note of the logic changes of the Q outputs of the D-type flip-flops 8 to 12, the number of logic changes is as shown in FIG. 10(h).
More specifically, at the rising edge timing of the fifth clock, when Q10 changes from high level to low level, Q11 simultaneously changes from low level to high level. Therefore, the number of logic changes is two. At the rising timing of the eleventh clock, when Q10 changes from high level to low level, Q12 simultaneously Changes from low level to high level, and hence the number of logic changes is two. At the rising timing of the seventeenth clock, too, the number of logic changes is two. At the other timings, however, the number of logic changes occurring simultaneously is one. Hence, the number of changes of the Q outputs of the flip-flops 8 to 12 is as shown in FIG. 10(h) .
In the driving circuit shown in FIG. 8, using the ring counter as shown in FIG. 9 as the second counter circuit 3, and decoding the voltage waveforms of the Q outputs of the D-type flip-flops 8 to 12 in the second logic circuit 6, signals in the vertical blanking period are generated.
This mode is explained below by reference to FIG. 11. FIG. 11 shows the output voltage waveform of the second logic circuit 6 in the driving circuit for solid-state image sensor shown in FIG. 8, the number of logic changes of the first and second counter circuits 2, 3, and the current changes.
FIG. 11(a ) denotes a composite blanking signal. It expressed the video period when the signal voltage is at low level, and the vertical blanking period and horizontal blanking period when the signal voltage is at high level.
The first counter circuit 2 measures the horizontal scanning period of the compound blanking period in FIG. 11(a) . The first counter circuit 2 does not stop measuring during its action period as understood from FIG. 11(b) .
Supposing here to realize the first counter circuit 2 by the counter circuit disclosed in the U.S. patent application Ser. No. 07/695,818 filed by the same applicant dated May 7, 1991, now U.S. Pat. No. 5,191,425 the number of logic changes of its output is constant as shown in FIG. 11(b) The output is, as mentioned above, delivered from the terminal 4 as the reference signal for horizontal scanning period.
On the other hand, the second counter circuit 3 measures the horizontal blanking period and vertical blanking period of the composite blanking signal in FIG. 11(a) , but in the video period, it is reset by the reset signal from the first logic circuit 5, and stops measuring. The reset is canceled by the reference signal for horizontal scanning period outputted from the first counter circuit 2.
Of the periods created in the second counter circuit 3, plural horizontal scanning periods including the final horizontal scanning period of the vertical blanking period are passed through a signal processing circuit (in particular, a circuit for delaying signals for the portion of one horizontal scanning period to the next one horizontal scanning period used in contour enhancing in the vertical direction or the like--hereinafter this is called 1 H delay line, and as a result, plural horizontal scanning periods including the final horizontal scanning periods of the vertical blanking period become plural horizontal scanning periods containing the first horizontal scanning period of the video period. FIG. 11(c) shows the number of logic changes of the output signal of the second counter circuit 3.
FIG. 11(d) indicates the current change caused when the signals for the portion of one horizontal scanning period are delayed to the next one horizontal scanning period by the 1 H delay line. However, the number of logic changes in FIG. 11(c) and the current change in FIG. 11(d) are mere examples, and in the actual circuit the number of logic changes and the number of current changes are greater than in the example in FIG. 11.
Nevertheless, in the driving circuit for solid-state image sensor shown in FIG. 8 as the elementary foundation of the invention, since the number of logic changes of the second counter circuit 3 is not uniform nonuniform power source current changes occur, and a fixed pattern noise is generated through the solid-state image sensor.
Since the second counter circuit 3 operates out of the video period, if a fixed pattern noise is generated, it does not matter directly in the video period. However, in the case of a specific signal processing, especially signal processing using 1 H delay line, a nonuniform current change as shown in FIG. 11(d) occurs in the first video period after the vertical blanking period. In consequence, spots of fixed pattern noise appear on the image field, in several horizontal scanning periods from the beginning of the video period.
It is hence a primary object of the invention to solve the above problems so that noise in the vertical blanking period may not appear in the video period even in the case of signal processing using 1 H delay line.
It is a further object of the invention to present a counter circuit comprising a logic circuit for adjusting the number of simultaneous changes for maintaining constant the number of simultaneous changes of logic circuit, and a logic circuit for adjusting the load capacitance for maintaining constant the load capacitance of outputs of measuring stages, being capable of inspecting for faults of the logic circuit for adjusting the number of simultaneous changes and the logic circuit for adjusting the load capacitance which do not influence the counting outputs.